About me

I am a Ph.D. student studying AI Accelerators and VLSI. I have been working in See Lab at UCSD CSE since Fall 2021.

I have taped-out two chips using TSMC CLN40LP (40 nm). The first chip is a hyper-dimensional computing (HDC) accelerator with a CNN feature extractor, capable of online few-shot learning. I am currently working on its post-silicon testing. The second chip replaces the HDC part with an in-ReRAM computing unit, which will come back from TSMC in Winter 2024.

Here is my CV.

Professional Experience

  • GPU Architecture Intern, Qualcomm (Summer 2023)

    Developed a visualizer for Ray-tracing acceleration structure.

Skill Set

Skills

  • Physical Design (Innovus, Virtuoso, Calibre)
  • RTL Design and Verification (VCS, DVE, Design Compiler, Formality)
  • Software Development (C/C++, CUDA, Python, Golang)
  • Other Software (Linux, Git, CMake)

Course Work

  • VLSI (EECS 312, EECS 427, EECS 627, UMich)
  • Computer Architecture (EECS 470, EECS 570, EECS 573, UMich)
  • Machine Learning/Python (CSE 250A, CSE 255, CSE 258, UCSD)
  • System Programming (CSE 237A, CSE 224, ECE 284, UCSD)

Portfolio